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Instructions, Operands, and Addressing
Instructions are operations performed by the CPU. Operands are entities operated upon by the instruction. Addresses are the locations in memory of specified data.
An instruction is a statement that is executed at runtime. An x86 instruction statement can consist of four parts:
Operands (instruction specific)
See Statements for the description of labels and comments.
The terms instruction and mnemonic are used interchangeably in this document to refer to the names of x86 instructions. Although the term opcode is sometimes used as a synonym for instruction, this document reserves the term opcode for the hexadecimal representation of the instruction value.
For most instructions, the Solaris x86 assembler mnemonics are the same as the Intel or AMD mnemonics. However, the Solaris x86 mnemonics might appear to be different because the Solaris mnemonics are suffixed with a one-character modifier that specifies the size of the instruction operands. That is, the Solaris assembler derives its operand type information from the instruction name and the suffix. If a mnemonic is specified with no type suffix, the operand type defaults to . Possible operand types and their instruction suffixes are:
Long (32–bit) (default)
The assembler recognizes the following suffixes for x87 floating-point instructions:
- [no suffix]
Instruction operands are registers only
Instruction operands are 64–bit
Instruction operands are 32–bit
See Chapter 3, Instruction Set Mapping for a mapping between Solaris x86 assembly language mnemonics and the equivalent Intel or AMD mnemonics.
An x86 instruction can have zero to three operands. Operands are separated by commas () (ASCII 0x2C). For instructions with two operands, the first (lefthand) operand is the source operand, and the second (righthand) operand is the destination operand (that is, source->destination).
The Intel assembler uses the opposite order (destination<-source) for operands.
Operands can be immediate (that is, constant expressions that evaluate to an inline value), register (a value in the processor number registers), or memory (a value stored in memory). An indirect operand contains the address of the actual operand value. Indirect operands are specified by prefixing the operand with an asterisk (*) (ASCII 0x2A). Only jump and call instructions can use indirect operands.
Immediate operands are prefixed with a dollar sign () (ASCII 0x24)
Register names are prefixed with a percent sign () (ASCII 0x25)
Memory operands are specified either by the name of a variable or by a register that contains the address of a variable. A variable name implies the address of a variable and instructs the computer to reference the contents of memory at that address. Memory references have the following syntax:.
is any of the x86 architecture segment registers. is optional: if specified, it must be separated from by a colon (). If is omitted, the value of (the default segment register) is assumed.
is the displacement from of the desired memory value. is optional.
and can be any of the general 32–bit number registers.
is a factor by which is to be multipled before being added to to specify the address of the operand. can have the value of 1, 2, 4, or 8. If is not specified, the default value is 1.
Some examples of memory addresses are:
Move the contents of memory location into number register .
Move the contents of memory location in the code segment (register ) into number register .
Move the address of into number register .
Add the address of memory location to the contents of number register to determine an address in memory. Move the contents of this address into number register .
Multiply the contents of number register by 4 and add the result to the contents of number register to produce a memory reference. Move the contents of this memory location into number register .
Multiply the contents of number register by 4, add the result to the contents of number register , and add the result to the address of to produce an address. Move the contents of this address into number register .
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